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INTEGRATED CIRCUITS
DATA SHEET
TDA8574 Class-H high-output voltage level line driver
Product specification Supersedes data of 1997 Feb 26 File under Integrated Circuits, IC01 1998 Oct 16
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
FEATURES * Output voltage swing larger than supply voltage * High supply voltage ripple rejection * Low distortion * Low noise * ESD protected on all pins. GENERAL DESCRIPTION The TDA8574(T) is a two channel class-H high-output voltage line driver for use in car audio applications. The line driver behaves as a non-inverting amplifier with a gain of 8 dB and a single-ended output. Due to the class-H voltage lifting principle the voltage swing over the load is more than the supply voltage. With a supply voltage of 9 V the output voltage swing over the load will be 14 V (peak-to-peak). QUICK REFERENCE DATA SYMBOL VCC ICC Gv Vo(rms) SVRR THD Vno Zo PARAMETER supply voltage supply current voltage gain maximal output voltage (RMS value) supply voltage ripple rejection total harmonic distortion noise output voltage output impedance Vo(rms) = 3 V; f = 1 kHz THD = 0.1% VCC = 9 V CONDITIONS 6 - 7.5 5.0 50 - - - MIN. 9 8 8 5.2 65 0.003 5 - TYP.
TDA8574
The TDA8574 is available in a DIP16 package and the TDA8574T in a SO16 package. Line drivers are necessary in car audio systems in which the power amplifiers are driven by long cables. The signal-to-noise ratio of these car audio systems is improved by using the TDA8574(T) class-H high-output level line driver. The high-output level of TDA8574(T) enables a reduction of the gain of the power amplifier resulting in an improvement of the power amplifier performance.
MAX. 12 13 8.5 - - - - 10
UNIT V mA dB V dB % V
ORDERING INFORMATION TYPE NUMBER TDA8574T TDA8574 PACKAGE NAME SO16 DIP16 DESCRIPTION plastic small outline package; 16 leads; body width 7.5 mm plastic dual in-line package; 16 leads (300 mil) VERSION SOT162-1 SOT38-4
1998 Oct 16
2
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
BLOCK DIAGRAM
TDA8574
handbook, full pagewidth
VCCL
1 36 k BUFFER 24 k VCCL 16 15 LIFT AMP. CL+ CL-
SVRL
3 BUFFER 30 k
- +
+ -
REFERENCE
SIGNAL AMP.
13
OUTL
VCCL
INL INML
2 4 14 LGND
INMR INR
5 7
TDA8574(T)
5 11 RGND
REFERENCE
VCCR
- +
12 SIGNAL AMP.
OUTR
30 k BUFFER SVRR 6 24 k BUFFER 8
+ -
LIFT AMP.
10 9
CR- CR+
VCCR 36 k
VCCR
MGE668
Fig.1 Block diagram.
1998 Oct 16
3
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
PINNING SYMBOL VCCL INL SVRL INML INMR SVRR INR VCCR CR+ CR- RGND OUTR OUTL LGND CL- CL+ PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION supply voltage left channel input voltage left channel SVRR left channel inverting input left channel inverting input right channel SVRR right channel input voltage right channel supply voltage right channel lift capacitor (+) right channel lift capacitor (-) right channel ground right channel output voltage right channel output voltage left channel ground left channel lift capacitor (-) left channel lift capacitor (+) left channel Fig.2 Pin configuration.
handbook, halfpage
TDA8574
VCCL INL SVRL INML INMR SVRR INR VCCR
1 2 3 4 5 6 7 8
MGE667
16 15 14
CL+ CL- LGND
13 OUTL TDA8574 TDA8574T 12 OUTR 11 10 9 RGND CR- CR+
FUNCTIONAL DESCRIPTION Lift amplifier The lift amplifier, referred to as LIFT AMP. in Fig.1, is used as a non-inverting amplifier with a voltage gain of 8 dB set by an internal feedback network. If the output voltage of the signal amplifier is low, the external lift capacitor is recharged by the lift amplifier. As soon as the output voltage of the signal amplifier increases above 0.87 x VCC the lift amplifier switches the voltage of the lift capacitor in series with the supply voltage VCC. The voltage at the positive side of the lift capacitor is referred to as lifted supply voltage. Signal amplifier The signal amplifier, referred to as SIGNAL AMP. in Fig.1, is used as a non-inverting amplifier. The voltage gain Gv is set by the feedback resistors according to the formula: R2 G v = 1 + -----R1 and should be set to 8 dB. The LIFT AMP. and SIG AMP. must have equal voltage gain Gv. The rail-to-rail output stage of the signal amplifier uses the lifted supply voltage to increase the output voltage swing.
The DC output level is set to 0.87 x VCC. The maximum peak-to-peak output voltage of the signal amplifier is calculated with the formula: V o ( p - p ) max 2 x ( 0.87V CC - 0.4 ) Buffers The buffers prevent loading of the internal voltage divider network made by a series connection of resistors. For a good supply voltage ripple rejection this internal voltage divider network has to be decoupled by an external capacitor. Reference This circuit supplies all currents needed in the device.
1998 Oct 16
4
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC IORM Tstg Tamb Tj PARAMETER supply voltage repetitive peak output current storage temperature operating ambient temperature junction temperature CONDITIONS operating - - -55 -40 - MIN.
TDA8574
MAX. 12 20 +150 +85 +150
UNIT V mA C C C
THERMAL CHARACTERISTICS SYMBOL Rth j-a TDA8574 (DIP16) TDA8574T (SO16) PARAMETER thermal resistance from junction to ambient in free air 75 110 K/W K/W VALUE UNIT
1998 Oct 16
5
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
DC CHARACTERISTICS VCC = 9 V; Tamb = 25 C; R L = 10 k; in accordance with application diagram (see Fig.3). SYMBOL VCC ICC VO Note 1. The DC output voltage with respect to ground is 0.87 x VCC. PARAMETER supply voltage supply current DC output voltage note 1 CONDITIONS Vin = 0 V 6 - - MIN. 9 8 7.8 TYP.
TDA8574
MAX. 12 13 -
UNIT V mA V
AC CHARACTERISTICS VCC = 9 V; f = 1 kHz; R L = 10 k; Tamb = 25 C; in accordance with test circuit (see Fig.3); note 1. SYMBOL Gv Gv cs flr fhr Zi Zo Vo(max)(rms) Vno THD + N SVRR PARAMETER voltage gain channel unbalance channel separation low frequency roll-off high frequency roll-off input impedance output impedance maximum output voltage (RMS value) noise output voltage total harmonic distortion plus noise THD + N = 0.1% unweighted; note 3 A-weighted; note 4 f = 1 kHz; Vo = 3 V (RMS); note 5 f = 17 Hz to 20 kHz; note 6 f = 20 Hz to 20 kHz; note 8 Notes 1. The channel separation is determined by the parasitic capacitance between the inverting input left channel (pin 4) and the inverting input right channel (pin 5). The PCB layout has a major contribution to the parasitic capacitance. To obtain best results, the PCB tracks to pin 4 and pin 5 should be separated as much as possible. 2. The frequency response is externally fixed by the input coupling capacitors. 3. Noise output voltage is measured in a bandwidth of 20 Hz to 20 kHz with a source resistor Rs = 600 . 4. Noise output voltage is measured in a bandwidth of 20 Hz to 20 kHz with an A-weighted filter with a source resistor Rs = 600 . 5. Distortion is measured at a frequency of 1 kHz using an A-weighted filter. 6. Distortion is measured at an output voltage of 3.0 V (RMS) at frequencies between 17 Hz and 20 kHz. 7. Ripple rejection is measured at the output, using a source resistor Rs = 600 and a ripple amplitude of 100 mV (RMS) at a frequency of 1 kHz. 8. Ripple rejection is measured at the output, using a source resistor Rs = 600 and a ripple amplitude of 100 mV (RMS) at frequencies between 20 Hz and 20 kHz. Rs = 600 ; Vo(rms) = 1 V; note 1 -1 dB; note 2 -1 dB CONDITIONS - 80 - 20 22 - 5.0 - - - - 50 - MIN. 7.5 8 - 90 - - 30 - 5.2 7 5 0.003 0.01 65 55 TYP. MAX. 8.5 0.5 - 5 - 38 10 - 9 - 0.01 - - - UNIT dB dB dB Hz kHz k V V V % % dB dB
supply voltage ripple rejection note 7
1998 Oct 16
6
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
APPLICATION INFORMATION
TDA8574
handbook, full pagewidth
24 k R1(1) VCC C6 100 nF
36 k R2(1) VCCL 1 36 k BUFFER 24 k SVRL 3 BUFFER 30 k VCCL 16 CL+ 15 CL- LIFT AMP. VCC C5 1.5 nF C4 100 F
- +
+ -
REFERENCE C1 22 F
SIGNAL AMP.
13 OUTL
C3 22 F RL 10 k
VCCL
INL 2 INML 4 14 LGND
INMR 5 C1 22 F REFERENCE Rs Rs INR 7
TDA8574(T)
5 11 RGND
VCCR
- +
12 OUTR SIGNAL AMP.
C3 22 F
RL 10 k
Vi(L)
Vi(R) 30 k BUFFER SVRR 6 C2 47 F VCCR 8 24 k BUFFER
+ -
LIFT AMP.
10 CR- 9 CR+
VCCR 36 k
C4 100 F C5 1.5 nF
VCC 24 k R1(1) 36 k R2(1)
MGE669
(1) R1 and R2 should have a tolerance of 1%.
Fig.3 Application diagram.
1998 Oct 16
7
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
Printed-Circuit Board (PCB) layout
TDA8574
handbook, full pagewidth
64
46.08
22 F OUTR 10 k SGND 22 F
22 F OUTL 10 k
SO16
22 F 24 k 36 k 24 k
SGND
INR 36 k RL 47 F VCC GND
INL
MBH883
Dimensions in mm. IC mounted on track side, additional components mounted on component side. Tracks viewed from component side.
Fig.4 Recommended PCB-layout.
1998 Oct 16
8
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
Application characteristics VCC = 9 V; RI = 10 k; Tamb = 25 C; 80 kHz filter.
TDA8574
handbook, halfpage
1
MGD906
handbook, halfpage
1
MGD907
THD + N (%) 10-1
THD + N (%) 10-1 f = 10 kHz Vo = 5 V 4V 3V 2V 10-2 1 kHz 100 Hz 0 2 4 V (V) o 6
10-2
10-3
10-3 10
102
103
104
f (Hz)
105
Fig.5
Total harmonic distortion plus noise as a function of Vo.
Fig.6
Total harmonic distortion plus noise as a function of frequency.
handbook, halfpage
10
MGD908
handbook, halfpage
-40
MGD909
G (dB) 8
SVRR (dB) -50 Rs = 600
6
-60 0
4
-70
2 10
102
103
104
105
f (Hz)
106
-80 10
102
103
104
f (Hz)
105
Fig.8 Fig.7 Total circuit gain as a function of frequency.
Supply voltage ripple rejection as a function of frequency.
1998 Oct 16
9
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
TDA8574
handbook, halfpage
-60
MGD910
handbook, halfpage
-60
MGD911
cs (dB)
-80
f = 10 kHz
cs (dB)
-80 1V
1 kHz 100 Hz
-100
-100
3V 5V
-120 0 1 2 3 4 Vo (V) 5
-120 10
102
103
104
f (Hz)
105
Fig.9 Channel separation as a function of Vo.
Fig.10 Channel separation as a function of frequency.
1998 Oct 16
10
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 7.5 mm
TDA8574
SOT162-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp L 1 e bp 8 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013AA EIAJ EUROPEAN PROJECTION A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 10.5 10.1 0.41 0.40 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
ISSUE DATE 95-01-24 97-05-22
1998 Oct 16
11
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
TDA8574
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.030
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1998 Oct 16
12
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
TDA8574
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Oct 16
13
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8574
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Oct 16
14
Philips Semiconductors
Product specification
Class-H high-output voltage level line driver
NOTES
TDA8574
1998 Oct 16
15
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/25/03/pp16
Date of release: 1998 Oct 16
Document order number:
9397 750 04393

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